The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Jun. 10, 2016
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

William Paul Hovis, Sammamish, WA (US);

Garrett Douglas Blankenburg, Sammamish, WA (US);

Peter Anthony Atkinson, Sammamish, WA (US);

Robert James Ray, Snoqualmie, WA (US);

Andres Felipe Hernandez Mojica, Seattle, WA (US);

Samy Boshra-Riad, Bellevue, WA (US);

Erng-Sing Wee, Bellevue, WA (US);

Brian Keith Langendorf, Benicia, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/3296 (2019.01); G06F 11/24 (2006.01); G06F 1/324 (2019.01); G06F 1/20 (2006.01); G06F 11/30 (2006.01); G06F 1/3206 (2019.01); G06F 1/28 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/206 (2013.01); G06F 1/28 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); G06F 11/24 (2013.01); G06F 11/3062 (2013.01); Y02D 10/126 (2018.01); Y02D 10/172 (2018.01);
Abstract

Voltage adjustment techniques for computing systems and processing devices are presented herein. In one example, a method of determining operating voltages for a processing device includes executing a voltage adjustment process to determine at least one input voltage for the processing device lower than a manufacturer specified operating voltage. During the voltage adjustment process, the method includes applying incrementally adjusted input voltages to the processing device, operating the processing device according to a functional test that exercises the processing device in context with associated system elements of a computing assembly, and monitoring for operational failures of at least the processing device during application of each of the incrementally adjusted input voltages. Responsive to the operational failures, the method includes determining corresponding values of the incrementally adjusted input voltages and establishing an input voltage based at least in part on the corresponding values of the incrementally adjusted input voltages.


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