The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2019

Filed:

Jan. 16, 2019
Applicant:

Samsung Display Co, Ltd., Yongin-si, Gyeonggi-do, KR;

Inventor:

Dong-Gyu Kim, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01); H01L 27/12 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); H01L 29/66 (2006.01); G02F 1/1343 (2006.01); H01L 29/786 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13454 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/13458 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1248 (2013.01); H01L 29/66765 (2013.01); H01L 29/78669 (2013.01); G02F 1/136227 (2013.01); G02F 2001/136295 (2013.01); G02F 2201/123 (2013.01); G02F 2201/50 (2013.01); G02F 2202/103 (2013.01); G09G 2300/0408 (2013.01);
Abstract

In an amorphous silicon thin film transistor-liquid crystal display device and a method of manufacturing the same, gate patterns including a gate line and a gate electrode are formed on an insulation substrate having a display region and a driving circuit region on which a plurality of shift resistors are formed. A gate insulating film, active layer patterns and data patterns including source/drain electrodes are formed successively on the substrate. A passivation layer on the substrate has a first contact hole exposing a drain electrode of the display region and second and third contact holes respectively exposing a gate electrode and source/drain electrode of a first transistor of each of the shift resistors. Electrode patterns on the passivation layer include a first electrode connected to the drain electrode of the display region through the first contact hole and a second electrode connecting the gate electrode to the source/drain electrode of the first transistor through the second and third contact holes. The gate driving circuit including the shift resistors and the wirings are integrated on the insulating substrate without an additional process, thereby simplifying the manufacturing process.


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