Method and apparatus for scan chain reordering and optimization in physical implementation of digital integrated circuits with on-chip test compression

Abstract

According to one general aspect, in a large digital integrated circuit with on-chip scan test compression hardware, an apparatus may include a digital circuit receiver circuit and a scan chain reorder circuit. The digital circuit receiver circuit configured to: receive a circuit model file that includes logic circuits that are represented by respective cells, wherein a plurality of cells are arranged in an ordered scan chain, and insert, in to the circuit model file, a dummy cell as an end cell at an end of the ordered scan chain. The scan chain reorder circuit configured to reorder the ordered scan chain to a reordered scan chain based, wherein the scan-chain reorder circuit is configured to maintain a start cell and an end cell of the ordered scan chain as a start cell and an end cell of the reordered scan chain.