The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2019
Filed:
Nov. 24, 2015
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/02 (2006.01); G01R 31/28 (2006.01); H01L 21/44 (2006.01); H01L 21/66 (2006.01); G01R 31/12 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2863 (2013.01); G01R 31/1227 (2013.01);
Abstract
A system has a chip mounting board and a docking board. The chip mounting board can be loaded with test samples in a low voltage environment and can then be transported to a high voltage environment. The chip mounting board can be connected to the docking board and allows high voltage testing of multiple samples in parallel. The chip mounting board can then be disconnected from the docking board and transported back to a low voltage environment to unload the tested samples.
Yehle, Joseph. (2019). System and method for high voltage stress testing plurality of parallel units (U.S. Patent No. 10338131). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10338131
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile