The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Dec. 04, 2015
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

John Laurence Pennock, Edinburgh, GB;

Tsjerk Hoekstra, Balerno, GB;

David Talmage Patten, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04R 19/00 (2006.01); H04R 1/04 (2006.01); H04R 1/28 (2006.01); H04R 19/04 (2006.01); H04R 31/00 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H04R 1/34 (2006.01);
U.S. Cl.
CPC ...
H04R 1/04 (2013.01); B81B 7/0061 (2013.01); B81C 1/00309 (2013.01); H04R 1/2853 (2013.01); H04R 19/005 (2013.01); H04R 19/04 (2013.01); H04R 31/00 (2013.01); H04R 31/003 (2013.01); B81B 2201/0257 (2013.01); B81B 2207/015 (2013.01); H04R 1/342 (2013.01); H04R 2201/003 (2013.01); H04R 2410/07 (2013.01);
Abstract

A MEMS transducer package () comprises a semiconductor die element () and a cap element (). The semiconductor die element () and cap element () have mating surfaces (). The semiconductor die element () and cap element () are configured such that when the semiconductor die element () and cap element () are conjoined, a first volume () is formed through the semiconductor die element () and into the semiconductor cap element (), and an acoustic channel is formed to provide an opening between a non-mating surface () of the semiconductor die element () and a side surface () of the transducer package.


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