The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

May. 24, 2017
Applicant:

Rohde & Schwarz Gmbh & Co. KG, München, DE;

Inventor:

Wolfgang Kufer, Mühldorf, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 7/06 (2006.01); G01S 7/42 (2006.01); H01Q 3/38 (2006.01); H03M 1/66 (2006.01); G06F 1/10 (2006.01); H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
H04B 7/0617 (2013.01); G01S 7/42 (2013.01); G06F 1/10 (2013.01); H01Q 3/38 (2013.01); H03M 1/0624 (2013.01); H03M 1/66 (2013.01);
Abstract

The invention relates to a method for controlling digital-to-analog converters (DAC), the method comprising: providing a plurality of digital-to-analog converters (DAC) of a multi-channel converter array wherein each DAC includes a separate clock generator; generating, by each clock generator, a RF carrier signal; converting, by each DAC, digital data signals into analog RF data signals based on the carrier signals of the corresponding clock generators; providing a separate control signal for each clock generator wherein the control signals comprise control information such that when the control signals are applied to the corresponding clock generators the different analog RF data signals provided at respective output terminals of each DAC comprise a pre-defined phase shift to each other; controlling the clock generator of each DAC directly and independently based on the provided control signals. The invention further relates to a converter arrangement RF transmit circuit arrangement.


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