The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Jan. 06, 2017
Applicant:

Thine Electronics, Inc., Tokyo, JP;

Inventors:

Yusuke Fujita, Tokyo, JP;

Shunichi Kubo, Tokyo, JP;

Yoshinobu Oshima, Tokyo, JP;

Assignee:

THINE ELECTRONICS, INC., Chiyoda-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 9/00 (2006.01); H03K 5/26 (2006.01); H03K 5/135 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
H03K 5/26 (2013.01); H03K 5/135 (2013.01); H03M 9/00 (2013.01); G11C 7/106 (2013.01);
Abstract

A serializer device () includes a first latch unit (), a second latch unit (), a conversion unit (), a frequency division unit (), a load signal generation unit (), a phase difference detection unit (), and a reset instruction unit (), and has a simple configuration and can reduce a bit error rate at an early stage. The phase difference detection unit () detects a phase difference between a first clock (CLK) applied to the first latch unit () and a third clock (CLK) applied to the second latch unit (). The reset instruction unit () outputs a reset instruction signal (RSTn) to the frequency division unit () when the phase difference is not within a target range.


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