The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Jun. 08, 2017
Applicant:

M31 Technology Corporation, Hsinchu County, TW;

Inventors:

Huai-Te Wang, Taoyuan, TW;

Chih Chien Hung, Hsinchu County, TW;

Assignee:

M31 Technology Corporation, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/1252 (2006.01); G06F 13/40 (2006.01); H04L 25/00 (2006.01); H04B 3/02 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1252 (2013.01); G06F 13/4027 (2013.01); G06F 13/4072 (2013.01); H04B 3/02 (2013.01); H04L 25/00 (2013.01);
Abstract

A circuit in a physical unit (PHY) is disclosed, the circuit comprising two trios and a combo wire therebetween, wherein each of said trios includes three wires, and wherein said combo wire is configurable as a signal, floating, or any dc voltage, furthermore, a Quad-IO block is designed for transmit data in two D-PHY lanes with the combo wire configured as a signal wire or a C-PHY trio with the combo wire configured as a shielding wire, such that the same Quad-IO block can be instantiated multiple times in a physical unit for meeting different bandwidth requirements as well as for placing pads along a same direction for preventing performance difference between D-PHY lanes or C-PHY trios.


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