The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2019
Filed:
Mar. 10, 2017
Applicant:
Socionext Inc., Yokohama-shi, Kanagawa, JP;
Inventors:
Ian Juso Dedic, Northolt, GB;
Abdullah Mohd. Riazuddin Ahmed, Maidenhead, GB;
Assignee:
SOCIONEXT INC., Yokohama, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G06F 3/05 (2006.01); H03B 5/12 (2006.01); H01L 29/94 (2006.01); H03B 27/00 (2006.01); H03K 5/135 (2006.01);
U.S. Cl.
CPC ...
H03B 5/1256 (2013.01); G06F 1/10 (2013.01); G06F 3/05 (2013.01); H01L 29/94 (2013.01); H03B 5/1293 (2013.01); H03B 27/00 (2013.01); H03K 5/135 (2013.01);
Abstract
There is disclosed herein integrated circuitry comprising a clock path for carrying a clock signal from a clock source to a circuit block, the circuit block being operable based on the clock signal. Clock buffer circuitry is provided along the clock path for buffering the clock signal. A tuneable inductance is connected to the clock path. A capacitor is connected to the clock path so as to form an AC coupling capacitor connected in series along the path, and is implemented between metal layers of the integrated circuitry.