The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2019
Filed:
Dec. 02, 2016
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Dong Yean Oh, Gyeonggi-do, KR;
Sang Yong Kim, Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/0228 (2013.01); H01L 21/285 (2013.01); H01L 21/30604 (2013.01); H01L 29/0649 (2013.01); H01L 29/4236 (2013.01); H01L 29/42364 (2013.01); H01L 29/66621 (2013.01); H01L 29/66666 (2013.01); H01L 29/78 (2013.01);
Abstract
A semiconductor integrated circuit device may include an isolating layer, a buried gate, source and drain regions, a dielectric layer having a high dielectric constant and an insulating interlayer. The isolating layer may be formed on a semiconductor substrate to define an active region. The buried gate may be formed in the active region of the semiconductor substrate. The source and drain regions may be formed in the active region at both sides of the buried gate. The dielectric layer may be configured to surround the source and drain regions. The insulating interlayer may be formed on the dielectric layer.