The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2019
Filed:
Jun. 21, 2016
Sharp Kabushiki Kaisha, Sakai, Osaka, JP;
Tetsuo Fujita, Sakai, JP;
Hajime Imai, Sakai, JP;
Hisao Ochi, Sakai, JP;
Tetsuo Kikuchi, Sakai, JP;
Hideki Kitagawa, Sakai, JP;
Masahiko Suzuki, Sakai, JP;
Shingo Kawashima, Sakai, JP;
Tohru Daitoh, Sakai, JP;
SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;
Abstract
A semiconductor device () is provided with a thin film transistor including an oxide semiconductor layer (), a gate electrode (), a gate insulating layer (), and a source electrode () and a drain electrode () that are in contact with the oxide semiconductor layer, at least one electrode of the source electrode (), the drain electrode (), and the gate electrode () has a multilayer structure that includes a first layer (A,A) containing copper and a second layer (B,B) containing titanium or molybdenum, the thickness of the first layer (A,A) is more than the thickness of the second layer (B,B), when the source electrode () or the drain electrode () has the multilayer structure, the second layer is arranged on the oxide semiconductor layer side of the first layer so as to be in contact with the surface of the oxide semiconductor layer (), when the gate electrode () has the multilayer structure, the second layer is arranged on the substrate () side of the first layer, and the thickness of the second layer is 15 nm or more and 25 nm or less.