The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Sep. 27, 2016
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Tsukasa Miura, Kanagawa, JP;

Shuji Manda, Kanagawa, JP;

Tomoyuki Hirano, Kanagawa, JP;

Junpei Yamamoto, Kanagawa, JP;

Kazunobu Ota, Nagasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 21/28 (2006.01); H01L 21/283 (2006.01); H01L 27/14 (2006.01); H04N 5/361 (2011.01); H04N 5/369 (2011.01); H01L 27/28 (2006.01); H01L 27/30 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1461 (2013.01); H01L 21/28 (2013.01); H01L 21/283 (2013.01); H01L 27/14 (2013.01); H01L 27/146 (2013.01); H01L 27/1469 (2013.01); H01L 27/14612 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14645 (2013.01); H01L 27/14689 (2013.01); H01L 27/286 (2013.01); H01L 27/307 (2013.01); H04N 5/361 (2013.01); H04N 5/369 (2013.01);
Abstract

The present disclosure relates to a solid-state image sensing device capable of restricting an occurrence of a dark current and a method for manufacturing the same, and an electronic device. A solid-state image sensing device includes a FD part formed on a P-type semiconductor substrate by implanting an N-type impurity, a high-dielectric insulative film laminated on at least the FD part, and a contact electrode connected to the FD part in a connection structure via the high-dielectric insulative film. For example, the high-dielectric insulative film is formed by use of a material which reduces the schottky barrier height in a connection part between the FD part and the electrode in a single layer or in a plurality of layers. The present technology is applicable to CMOS image sensors, for example.


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