The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Aug. 31, 2015
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Boe Optoelectronics Technology Co., Ltd., Anhui, CN;

Inventors:

Xiaobin Yin, Beijing, CN;

Chuanbao Chen, Beijing, CN;

Dongling Sun, Beijing, CN;

Lisen Wang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/136 (2006.01); H01L 27/12 (2006.01); H01L 27/32 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1244 (2013.01); G02F 1/1368 (2013.01); G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); G02F 1/134309 (2013.01); G02F 1/136227 (2013.01); G02F 1/136286 (2013.01); H01L 27/1222 (2013.01); H01L 27/1248 (2013.01); H01L 27/3248 (2013.01); H01L 29/41733 (2013.01); H01L 29/78606 (2013.01); H01L 29/78618 (2013.01); G02F 2001/13606 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01); H01L 27/3223 (2013.01); H01L 27/3262 (2013.01);
Abstract

The present disclosure provides a pixel unit and a method for producing the same, an array substrate and a display apparatus. The pixel unit includes: a thin film transistor; an insulation layer formed at least on a drain electrode of the thin film transistor and formed therein with a via hole which extends through the insulation layer to expose the drain electrode of the thin film transistor below the insulation layer; a pixel electrode formed on the insulation layer and electrically connected to the drain electrode of the thin film transistor at the via hole; and at least one elevating layer formed below the via hole and located below a part of the drain electrode exposed from the via hole such that the exposed part has a height greater than the height of the parts of the drain electrode adjacent to the exposed part. The depth and slope of the via hole is reduced by adding the elevating layer below the via hole. The elevating layer may be made from the gate metal layer and/or the active layer that are not etched off in process without increasing any production cost and process difficulty.


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