The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Nov. 07, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yunghwan Son, Hwaseong-si, KR;

Jaesung Sim, Hwaseong-si, KR;

Shinhwan Kang, Seoul, KR;

Youngwoo Park, Seoul, KR;

Jaeduk Lee, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11575 (2017.01); H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); H01L 29/34 (2006.01); H01L 27/11526 (2017.01); G11C 5/02 (2006.01); G11C 16/04 (2006.01); H01L 27/11517 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11548 (2017.01); H01L 27/11556 (2017.01); G11C 16/30 (2006.01); H01L 27/11551 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11575 (2013.01); G11C 5/025 (2013.01); G11C 16/0483 (2013.01); H01L 27/1157 (2013.01); H01L 27/11517 (2013.01); H01L 27/11526 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); H01L 29/34 (2013.01); G11C 16/30 (2013.01); H01L 27/11551 (2013.01);
Abstract

A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.


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