The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Aug. 17, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Mustafa Badaroglu, Kessel-Lo, BE;

Kern Rim, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/02 (2006.01); H01L 27/11 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/30625 (2013.01); H01L 21/76224 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0207 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 21/823475 (2013.01); H01L 27/1104 (2013.01);
Abstract

Integrating a gate-all-around (GAA) field-effect transistor(s) and a FinFET(s) on a common substrate of a semiconductor die is disclosed. GAA FETs and FinFETs can form integrated circuits (ICs). GAA FETs and FinFETs are integrated on a common substrate to optimize advantages of each type of FET. For example, FinFETs may be formed in the common substrate in the semiconductor die for forming circuits where reduced resistance and capacitance are important for performance, whereas GAA FETs may be formed in the common substrate in the semiconductor die for forming circuits with decreased threshold voltage to allow voltage scaling to lower supply voltages to reduce power consumption and also to reduce silicon area as a result of vertically stacked devices. This supports a designer having the freedom to separate control the channel width of the GAA FETs and FinFETs, which may be important for controlling drive strength and/or area for different circuits.


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