The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

May. 20, 2016
Applicant:

Infineon Technologies Americas Corp., El Segundo, CA (US);

Inventors:

Eung San Cho, Torrance, CA (US);

Parviz Parto, Laguna Niguel, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2006.01); H01L 49/02 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 21/4853 (2013.01); H01L 23/495 (2013.01); H01L 23/49534 (2013.01); H01L 23/49537 (2013.01); H01L 24/17 (2013.01); H01L 25/16 (2013.01); H01L 28/10 (2013.01); H01L 23/3107 (2013.01); H01L 23/49551 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/16245 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1425 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19104 (2013.01);
Abstract

In one implementation, a semiconductor package includes an integrated circuit (IC) flip chip mounted on a first patterned conductive carrier, a second patterned conductive carrier situated over the IC, and a magnetic material situated over the second patterned conductive carrier. The semiconductor package also includes a third patterned conductive carrier situated over the magnetic material. The second patterned conductive carrier and the third patterned conductive carrier are electrically coupled so as to form windings of an integrated inductor in the semiconductor package.


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