The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2019
Filed:
Feb. 14, 2018
Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;
Stmicroelectronics (Crolles 2) Sas, Crolles, FR;
Stmicroelectronics (Rousset) Sas, Rousset, FR;
Franck Julien, La Penne sur Huveaune, FR;
Stephan Niel, Meylan, FR;
Emmanuel Richard, Saint Pierre d'Allevard, FR;
Olivier Weber, Grenoble, FR;
STMICROELECTRONICS (ROUSSET) SAS, Rousset, FR;
STMICROELECTRONICS (CROLLES 2) SAS, Crolles, FR;
COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris, FR;
Abstract
A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.