The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Jan. 12, 2018
Applicants:

Inventec (Pudong) Technology Corporation, Shanghai, CN;

Inventec Corporation, Taipei, TW;

Inventor:

Ying-Xian Han, Shanghai, CN;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 16/12 (2006.01); G06F 13/16 (2006.01); G06F 9/445 (2018.01); G11C 16/04 (2006.01); G11C 29/02 (2006.01); H01L 27/24 (2006.01); G11C 16/34 (2006.01); G06F 21/73 (2013.01); G11C 5/14 (2006.01); G11C 16/10 (2006.01); G11C 16/22 (2006.01); G11C 16/30 (2006.01); G11C 7/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/12 (2013.01); G06F 9/445 (2013.01); G06F 13/16 (2013.01); G06F 21/73 (2013.01); G11C 5/14 (2013.01); G11C 5/144 (2013.01); G11C 7/24 (2013.01); G11C 16/04 (2013.01); G11C 16/102 (2013.01); G11C 16/22 (2013.01); G11C 16/225 (2013.01); G11C 16/30 (2013.01); G11C 16/3459 (2013.01); G11C 29/023 (2013.01); H01L 27/2436 (2013.01);
Abstract

A chip programming device comprises a chip socket and a protecting circuit. The chip socket is configured to accommodate a chip to be programmed, is electrically connected with a circuit board, and comprises a power terminal and a ground terminal which are configured to connect to the chip. The protecting circuit is disposed on the circuit board, and comprises a power input terminal, an enable signal input terminal and a power output terminal which is electrically connected to the power terminal of the chip socket. The protecting circuit receives a power signal via the power input terminal, receives an enable signal via the enable signal input terminal, provides the power signal to the chip socket via the power output terminal when the enable signal has a first electric potential, and terminates the power signal to the chip socket when the enable signal has a second electric potential.


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