The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Nov. 21, 2017
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventor:

Chia-Wei Wang, Taichung, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/10 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 8/06 (2006.01); G11C 8/18 (2006.01); G06F 17/50 (2006.01); G11C 7/12 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G06F 17/5045 (2013.01); G11C 7/1006 (2013.01); G11C 7/109 (2013.01); G11C 7/1078 (2013.01); G11C 7/1093 (2013.01); G11C 7/12 (2013.01); G11C 8/06 (2013.01); G11C 8/18 (2013.01); G06F 13/1689 (2013.01);
Abstract

An embedded memory includes a memory interface circuit, a cell array, and a peripheral circuit. The memory interface circuit receives at least a clock signal, a non-clock signal, and a setup-hold time control setting, and includes a programmable path delay circuit that is used to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting. The clock path is used to deliver the clock signal, and the non-clock path is used to deliver the non-clock signal. The peripheral circuit is used to access the cell array according to at least the clock signal provided from the clock path and the non-clock signal.


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