The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Apr. 12, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Soo-Ho Cha, Seoul, KR;

Chankyung Kim, Hwaseong-si, KR;

Sungchul Park, Seoul, KR;

Hoyoung Song, Hwaseong-si, KR;

Kwangchol Choe, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 7/12 (2006.01); G11C 7/06 (2006.01); G11C 7/14 (2006.01); G11C 7/22 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/4099 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/062 (2013.01); G11C 7/14 (2013.01); G11C 7/22 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/4099 (2013.01); G11C 11/565 (2013.01); G11C 7/065 (2013.01);
Abstract

A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.


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