The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2019
Filed:
Jun. 22, 2017
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06G 7/62 (2006.01); H03K 19/00 (2006.01); H01L 23/58 (2006.01); G01R 31/28 (2006.01); H01L 29/10 (2006.01); H01L 25/00 (2006.01); G01R 27/28 (2006.01); G01R 31/36 (2019.01);
U.S. Cl.
CPC ...
G06F 17/5031 (2013.01); G06F 17/5045 (2013.01); G06F 17/5081 (2013.01); G01R 27/28 (2013.01); G01R 31/28 (2013.01); G01R 31/36 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06G 7/62 (2013.01); H01L 23/58 (2013.01); H01L 25/00 (2013.01); H01L 29/10 (2013.01); H03K 19/00 (2013.01);
Abstract
A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.