The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Oct. 19, 2012
Applicant:

Arm Norway As, Trondheim, NO;

Inventors:

Jorn Nystad, Trondheim, NO;

Edvard Sorgard, Trondheim, NO;

Borgar Ljosland, Trondheim, NO;

Mario Blazevic, Lena, NO;

Assignee:

ARM Norway AS, Trondheim, NO;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06F 12/14 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 9/54 (2006.01); G06F 12/10 (2016.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 9/54 (2013.01); G06F 12/10 (2013.01); G06F 13/1673 (2013.01); G06F 13/4068 (2013.01); G06F 13/4221 (2013.01); G06T 1/20 (2013.01); G06F 2212/1052 (2013.01);
Abstract

A slave device communicates with a host system via a host communications bus. The host system includes one processing unit that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processing unit and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the 'internal' physical address of the slave's resources and forwards the access to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.


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