The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Jan. 03, 2017
Applicant:

National Instruments Corporation, Austin, TX (US);

Inventors:

Tai A. Ly, Austin, TX (US);

Swapnil D. Mhaske, Highland Park, NJ (US);

Hojin Kee, Austin, TX (US);

Adam T. Arnesen, Pflugerville, TX (US);

David C. Uliana, Austin, TX (US);

Newton G. Petersen, Emporia, KS (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); H03M 13/11 (2006.01); G06F 11/10 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0616 (2013.01); G06F 3/064 (2013.01); G06F 3/0604 (2013.01); G06F 3/0622 (2013.01); G06F 3/0659 (2013.01); G06F 3/0661 (2013.01); G06F 3/0673 (2013.01); G06F 11/1076 (2013.01); G06F 13/1615 (2013.01); G06F 13/1626 (2013.01); G11C 7/1039 (2013.01); H03M 13/1102 (2013.01); H03M 13/114 (2013.01); H03M 13/1105 (2013.01); H03M 13/6563 (2013.01); H03M 13/6566 (2013.01); H03M 13/6569 (2013.01); Y02D 10/14 (2018.01);
Abstract

Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.


Find Patent Forward Citations

Loading…