The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2019

Filed:

Feb. 19, 2016
Applicant:

Khalifa University of Science and Technology, Abu Dhabi, AE;

Inventors:

Jerald Yoo, Abu Dhabi, AE;

Muhammad Altaf, Abu Dhabi, AE;

Chen Zhang, Abu Dhabi, AE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
A61B 5/00 (2006.01); A61B 5/04 (2006.01); A61N 1/36 (2006.01); A61B 5/053 (2006.01); A61B 5/0478 (2006.01); G16H 50/20 (2018.01); G06F 19/00 (2018.01);
U.S. Cl.
CPC ...
A61B 5/4094 (2013.01); A61B 5/0478 (2013.01); A61B 5/0531 (2013.01); A61N 1/36025 (2013.01); G06F 19/00 (2013.01); G16H 50/20 (2018.01); A61B 5/6814 (2013.01); A61B 2560/0209 (2013.01); A61B 2562/164 (2013.01); A61N 1/36064 (2013.01);
Abstract

A SoC includes an AFE to receive a plurality of differential input channels and generate digitized data corresponding to the channels, and a classification processor configured to receive the digitized data from the AFE. The AFE includes a Dual-Channel Chopper to perform channel multiplexing of two channels while simultaneously chopping the channels, a Dual Channel Charge Recycled-AFE having an Chopper-Stabilized Capacitive-Coupled IA including bias sampling capacitors that store bias values associated with the first and second channels to enable swapping between the channel, and a DC servo loop (DSL) having a reduced setting time based on a reduction in a resistance of the pseudo-PMOS in response to engaging a system reset. The classification processor includes a Frequency-Time Division Multiplexing (FTDM) Feature Extraction (FE) engine and a Dual-Detector Architecture (DA) classification processor. The FTDM-FE includes a plurality of FIFOs configured to store, in parallel, the digitized data corresponding to the channels, a plurality of BPF banks storing BPF coefficients, and a single BPF to calculate outputs of one specific bank of the BFP banks for all of the channels. The DA processor receives the output from the FTDM-FE and estimates a beginning and end of a seizure using two LSVMs optimized for only sensitivity and specificity, respectively.


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