The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Mar. 30, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Pratik Rajeshbhai Patel, Bangalore, IN;

Percy Tehmul Marfatia, Bangalore, IN;

Rajagopal Narayanan, Bangalore, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/082 (2006.01); H03K 3/356 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356113 (2013.01); H03K 19/018521 (2013.01);
Abstract

A novel clock level-shifter to reduce duty-cycle distortion across wide input-output voltage operating range is disclosed. In some implementations, a level shifter includes an input stage coupled to a first power supply to receive an input signal, an output stage coupled to a second power supply to generate an output signal, and a first switch coupled directly between the output stage and the second power supply, wherein the input signal turns on or off the first switch. In some implementations, the first switch has a gate, a source, and a drain, the source being coupled to the second power supply, the drain being coupled to the output stage, and the gate being driven directly by the input signal.


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