The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

May. 17, 2018
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza (MB), IT;

Inventors:

Stefano Ramorini, Arluno, IT;

Alberto Cattani, Cislago, IT;

Alessandro Gasparini, Cusano Milanino, IT;

Germano Nicollini, Piacenza, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza (MB), IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03F 3/45 (2006.01); H03M 1/12 (2006.01); H03M 1/68 (2006.01); H03M 1/74 (2006.01); H03M 1/76 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45192 (2013.01); H03M 1/124 (2013.01); H03M 1/66 (2013.01); H03F 2200/18 (2013.01); H03M 1/68 (2013.01); H03M 1/742 (2013.01); H03M 1/765 (2013.01);
Abstract

A circuit includes an input transistor pair with first and second input transistors, the first input transistor having a control terminal configured to receive an input signal and a cascode transistor pair including a first and second cascode transistors having a common control node. A bias circuit has a bias input configured to receive the input signal and a first bias output coupled to the common node of the first and second cascode transistors. The bias circuit includes a signal tracking circuit operating to generate the first bias output to track the input signal. A pair of load transistors are coupled to the input transistor pair and biased by a second bias output of the bias circuit.


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