The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Oct. 11, 2017
Applicant:

Telefonaktiebolaget Lm Ericsson (Publ), Stockholm, SE;

Inventors:

Daniele Mastantuono, Lund, SE;

Sven Mattisson, Bjärred, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 1/26 (2006.01); H03F 1/32 (2006.01); H03F 3/193 (2006.01); H03F 1/02 (2006.01); H03F 1/48 (2006.01); H03F 3/60 (2006.01); H04B 1/12 (2006.01);
U.S. Cl.
CPC ...
H03F 1/26 (2013.01); H03F 1/0205 (2013.01); H03F 1/3211 (2013.01); H03F 1/483 (2013.01); H03F 3/193 (2013.01); H03F 3/45179 (2013.01); H03F 3/607 (2013.01); H03F 2200/06 (2013.01); H03F 2200/294 (2013.01); H03F 2200/333 (2013.01); H03F 2200/451 (2013.01); H03F 2203/45306 (2013.01); H03F 2203/45318 (2013.01); H04B 1/12 (2013.01);
Abstract

Systems and methods of noise suppression by an amplifier are presented. In one exemplary embodiment, an amplifier comprises first and fourth transistors configured as a first differential pair of transistors in a common-gate configuration, and second and third transistors configured as a second differential pair of transistors in a common-source configuration. The first and fourth transistors are operative to receive, from a differential input, by a source of each first and fourth transistor, a differential input signal. Further, a drain of each first and fourth transistor is coupled to respective first and second outputs configured as a differential output. The second and third transistors are operative to output, from a drain of each second and third transistor, to the respective second and first outputs, a differential output signal. Further, a gate of each second and third transistor is coupled to the respective first and second inputs.


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