The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2019
Filed:
Nov. 21, 2017
Microchip Technology Incorporated, Chandler, AZ (US);
Greg Dix, Tempe, AZ (US);
Jina Shumate, Phoenix, AZ (US);
Eric Peterson, Tempe, AZ (US);
Rajesh Nayak, Phoenix, AZ (US);
MICROCHIP TECHNOLOGY INCORPORATED, Chandler, AZ (US);
Abstract
A method is provided for forming an integrated circuit (IC) structure including trench-based semiconductor devices, e.g., trench FETs, having front-side drain contacts. The method may include forming an epitaxy region, forming a poly gate trench in the epitaxy region, forming a drain contact trench through the poly gate trench and extending below the poly gate trench, forming a poly gate in the poly gate trench, forming a front-side drain contact in the drain contact trench, and forming a source region in the epitaxy region adjacent the poly gate. The device may define a drift region from the poly gate/source intersection to the front-side drain contact. The drift region may be located within the epitaxy layer, without extending into an underlying substrate or transition layer. The front-side drain contact depth may be selected to influence the device breakdown voltage. The front-side drain contacts may allow flip-chip mounting of the IC structure.