The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Sep. 06, 2017
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Kotaro Noda, Mie, JP;

Mutsumi Okajima, Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/249 (2013.01); H01L 27/2436 (2013.01); H01L 27/2454 (2013.01); H01L 45/1683 (2013.01); H01L 45/04 (2013.01); H01L 45/1226 (2013.01); H01L 45/146 (2013.01);
Abstract

A memory device includes a first interconnect extending in a first direction, semiconductor members extending in a second direction, a second interconnect provided between the semiconductor members and extending in a third direction, a first insulating film provided between the semiconductor member and the second interconnect, third interconnects extending in the second direction, fourth interconnects provided between the third interconnects and arranged along the second direction, a resistance change film provided between the third interconnect and the fourth interconnects, and a first film. The first film is provided between the second interconnect and the fourth interconnect, interposes between the semiconductor member and the resistance change film, and not interpose between the semiconductor member and the third interconnect connected to each other. A first end of the semiconductor member is connected to the first interconnect. The third interconnect is connected to a second end of the semiconductor member.


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