The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Feb. 23, 2015
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Youngjang Lee, Seoul, KR;

Kyungmo Son, Gyeonggi-do, KR;

Sohyung Lee, Gyeonggi-do, KR;

Moonho Park, Seoul, KR;

Sungjin Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 27/32 (2006.01); H01L 29/04 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H01L 21/822 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1251 (2013.01); G02F 1/1368 (2013.01); G02F 1/13624 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/3244 (2013.01); H01L 29/04 (2013.01); H01L 29/7869 (2013.01); H01L 29/78675 (2013.01); G02F 2001/13685 (2013.01); H01L 21/8221 (2013.01); H01L 27/1214 (2013.01);
Abstract

The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate. A thin film transistor substrate includes a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode over the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the substrate, the second thin film transistor including a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed over the first gate electrode and the second gate electrode and under the oxide semiconductor layer.


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