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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10325882 B1

PDFFull Text
Date of Patent:
Jun. 18, 2019

Filed:

Jul. 17, 2017

Method of manufacturing semiconductor package

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Tae-woo Kang, Suwon-si, KR;

Byung-lyul Park, Seoul, KR;

Kyoung-hwan Kim, Yongin-si, KR;

Kun-sang Park, Hwaseong-si, KR;

Young-gyu Ahn, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Bradley Smith

Assistant Examiner:

David J Goodwin

Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 25/065 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/02063 (2013.01); H01L 21/0274 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/563 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/13 (2013.01); H01L 23/3135 (2013.01); H01L 23/3142 (2013.01); H01L 23/498 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 25/50 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16145 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method of manufacturing a semiconductor package includes providing a substrate including a mounting region having a recess space for accommodating a semiconductor chip and a connection region surrounding the mounting region, providing a semiconductor chip in the mounting region, the semiconductor chip including a connection pad provided on a top surface of the semiconductor chip, forming a protective layer covering a top surface of the substrate and the top surface of the semiconductor chip, forming a photosensitive insulating layer on the protective layer after forming the protective layer, patterning the photosensitive insulating layer thereby exposing the protective layer, removing the exposed protective layer, and forming a redistribution line to be electrically connected to the connection pad.

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