The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Mar. 16, 2018
Applicants:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporartion, Minato-ku, Tokyo, JP;

Inventor:

Kaoru Hama, Yokohama Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0433 (2013.01); G11C 16/26 (2013.01);
Abstract

In a semiconductor memory device of an embodiment, a write circuit includes an inversion circuit configured to invert write data and output the inverted write data, a first switch configured to pass or stop a current for programming a first memory cell in the first memory cell array to a selected bit line of the first memory cell array, a second switch configured to pass or stop a current for programming a second memory cell in the second memory cell array to a selected bit line of the second memory cell array, and a gate circuit configured to program one of the first memory cell and the second memory cell, and unprogram another of the first memory cell and the second memory cell simultaneously, by controlling the first switch based on the write data and controlling the second switch based on the inverted write data.


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