The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2019
Filed:
Sep. 15, 2015
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventor:
Stephen M. Trimberger, Incline Village, NV (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G11C 11/413 (2006.01); H03K 19/177 (2006.01); H03K 19/003 (2006.01); G06F 21/75 (2013.01); G06F 21/76 (2013.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 11/413 (2013.01); G06F 21/75 (2013.01); G06F 21/76 (2013.01); G11C 5/14 (2013.01); H03K 19/003 (2013.01); H03K 19/1776 (2013.01);
Abstract
The disclosure describes approaches for generating a physically unclonable function (PUF) value. Power is applied to a power control circuit, an SRAM, and a PUF control circuit. After initially powering-up the SRAM, the PUF control circuit signals the power control circuit to disable power to the SRAM. The power control circuit disables power to the SRAM, and then re-enables power to the SRAM after having power to the SRAM disabled for a waiting period. The PUF control circuit reads a PUF value from the SRAM by the PUF control circuit after the enabling of power.