The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Jan. 12, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Jong-Hoon Lee, Hwaseong-si, KR;

Eun-Suk Cho, Suwon-si, KR;

Woo-Pyo Jeong, Seoul, KR;

Sang-Wan Nam, Hwaseong-si, KR;

Jung-Ho Song, Anyang-si, KR;

Yun-Ho Hong, Hwaseong-si, KR;

Jae-Hoon Lee, Daejeon, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G06F 3/06 (2006.01); H01L 27/02 (2006.01); H01L 21/265 (2006.01); G11C 7/10 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/32 (2006.01); H01L 27/11582 (2017.01); H01L 27/11573 (2017.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G11C 7/106 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); H01L 21/265 (2013.01); H01L 27/0207 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01);
Abstract

A non-volatile memory device includes a memory cell array region in which memory cells are vertically stacked on a substrate and a page buffer region in which first and second page buffers are arranged. A first distance between the memory cell array region and the first page buffer is shorter than a second distance between the memory cell array region and the second page buffer. The first page buffer includes a first transistor driven in response to a first control signal. The second page buffer includes a second transistor driven in response to a second control signal corresponding to the first control signal. At least one of design constraints and processing constraints with respect to the first and second transistors is different.


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