The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Jun. 21, 2016
Applicant:

Lsis Co., Ltd., Gyeonggi-do, KR;

Inventors:

Geon Yoon, Gyeonggi-do, KR;

Ki-Myung Kim, Gyeonggi-do, KR;

Assignee:

LSIS CO., LTD., Anyang-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 19/05 (2006.01); H04L 29/08 (2006.01);
U.S. Cl.
CPC ...
G05B 19/052 (2013.01); G05B 19/056 (2013.01); H04L 69/324 (2013.01); G05B 2219/1205 (2013.01); G05B 2219/15112 (2013.01); G05B 2219/2639 (2013.01);
Abstract

In some embodiments, a PLC system including a first CPU comprising a first media access control (MAC) communications layer and configured to generate data necessary for operation of the CPU, perform control operation based on the generated data, and transmit the generated data to a second CPU via the first MAC communications layer is included. The PLC system may further include the second CPU comprising a second MAC communications layer receiving the generated data via the first MAC communications layer and configured to perform service operation based on the received data. The first CPU may be connected to a memory in which data to be transmitted to the second CPU is stored at a predetermined location, and the second CPU may receive the data stored in the predetermined location of the memory by a direct memory access (DMA) scheme.


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