The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2019
Filed:
Jan. 16, 2018
Qualcomm Incorporated, San Diego, CA (US);
Lesly Endrinal, San Diego, CA (US);
Rakesh Kinger, San Diego, CA (US);
Joseph Fang, San Diego, CA (US);
Srinivas Patil, Austin, TX (US);
Lavakumar Ranganathan, San Diego, CA (US);
Chia-Ying Chen, San Diego, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
The present disclosure provide techniques for semiconductor testing, and more particularly, to systems and methods for laser-based fault isolation and design for testability (DFT) diagnosis techniques. In one embodiment, an integrated chip (IC) testing apparatus, includes an input pin; a decompressor connected to the input pin; a plurality of scan chains, each scan chain of the plurality of scan chains comprising a plurality of scan cells; a plurality of scan chain control elements, each scan chain control element of the plurality of scan chain control elements being connected between the decompressor and a respective scan chain of the plurality of scan chains, wherein each scan chain control element is configured to enable or disable test data from flowing from the compressor to the respective scan chain; a compressor connected to an output of each scan chain of the plurality of scan chains; and an output pin connected to the compressor.