The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Mar. 14, 2016
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Vamsikrishna Parupalli, Austin, TX (US);

Itisha Tyagi, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/00 (2006.01); G01R 19/10 (2006.01); H03F 3/45 (2006.01); H03F 1/02 (2006.01); H04R 3/00 (2006.01); G01R 15/14 (2006.01);
U.S. Cl.
CPC ...
G01R 19/10 (2013.01); H03F 1/0205 (2013.01); H03F 3/45 (2013.01); H03F 3/45475 (2013.01); H03F 3/45937 (2013.01); G01R 15/14 (2013.01); H03F 2200/171 (2013.01); H03F 2200/462 (2013.01); H03F 2203/45048 (2013.01); H03F 2203/45081 (2013.01); H03F 2203/45101 (2013.01); H04R 3/007 (2013.01);
Abstract

The overall performance of a current sense amplifier system may be improved by increasing the common mode rejection of the system. In particular, improved current sense amplifiers may be configured to use a first signal path coupled to the amplifier and a first input terminal, wherein the first signal path is configured to measure the current through a device by generating a voltage proportional to the measured current, wherein the generated voltage includes a small signal voltage with a large common mode voltage, and a second signal path coupled to the amplifier and the first input terminal, wherein the second signal path is configured to reduce the common mode of the generated voltage by level shifting the generated voltage to reduce the common mode voltage.


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