The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2019

Filed:

Nov. 17, 2016
Applicant:

Murata Manufacturing Co., Ltd., Nagaokakyo-shi, Kyoto, JP;

Inventor:

Lasse Aaltonen, Espoo, FI;

Assignee:

MURATA MANUFACTURING CO., LTD., Nagaokakyo-Shi, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 27/26 (2006.01); G01C 25/00 (2006.01); B81C 99/00 (2010.01); G01C 19/5712 (2012.01); G01P 15/125 (2006.01); G01P 21/00 (2006.01);
U.S. Cl.
CPC ...
G01C 25/00 (2013.01); B81C 99/0035 (2013.01); G01C 19/5712 (2013.01); G01P 15/125 (2013.01); G01P 21/00 (2013.01);
Abstract

A discrete-time high voltage generating circuitry is described, configured to provide a discrete-time high voltage at a high voltage output only during defined high voltage periods. The discrete-time high voltage generating circuitry includes a current mirror circuitry configured to receive a supply current from a high voltage source and to provide a slew current. The discrete-time high voltage generating circuitry is configured to generate the discrete-time high voltage using the slew current. Further, a method to operate a discrete-time high voltage generating circuitry is described. The circuitry and method may be used to provide a discrete-time self-test bias voltage to at least one capacitive load such as a capacitive MEMS element.


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