The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Sep. 01, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Yue Li, San Diego, CA (US);

Charles David Paynter, Encinitas, CA (US);

Ryan David Lane, San Diego, CA (US);

Ruey Kae Zang, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H05K 1/03 (2006.01); H05K 1/11 (2006.01); H01L 23/64 (2006.01); H01L 21/48 (2006.01); H01L 23/13 (2006.01); H01L 23/16 (2006.01);
U.S. Cl.
CPC ...
H05K 1/186 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/64 (2013.01); H05K 1/0306 (2013.01); H05K 1/0313 (2013.01); H05K 1/113 (2013.01); H05K 1/114 (2013.01); H01L 23/13 (2013.01); H01L 23/16 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19106 (2013.01); H05K 2201/1003 (2013.01); H05K 2201/10015 (2013.01);
Abstract

An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer.


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