The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Nov. 04, 2016
Applicant:

Teledyne E2v Semiconductors Sas, Saint Egrève, FR;

Inventors:

Etienne Bouin, Brignoud, FR;

Rémi Laube, Veurey-voroize, FR;

Jérôme Ligozat, Grenoble, FR;

Marc Stackler, St Martin le Vinoux, FR;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/00 (2006.01); H03M 1/06 (2006.01); H03M 1/12 (2006.01); H04L 7/00 (2006.01); H03K 5/1534 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0624 (2013.01); H03K 5/1534 (2013.01); H03M 1/123 (2013.01); H04L 7/0008 (2013.01); H03K 2005/00267 (2013.01); H03M 1/1215 (2013.01);
Abstract

In an architecture for processing data comprising a control unit and converters CNto be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgethat sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter. A phase parameter Sel-shiftfurthermore allows the phase of the sampling clocks of n converting cores of the converters, working at a sampling frequency obtained by dividing by n the CLK reference-clock frequency, to be synchronized.


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