The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Oct. 04, 2017
Applicant:

Rohm Co., Ltd., Kyoto-shi, Kyoto, JP;

Inventors:

Hirotaka Otake, Kyoto, JP;

Tatsuya Yanagi, Kyoto, JP;

Yusuke Nakakohara, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H01L 23/10 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H03K 17/041 (2006.01); H01L 23/495 (2006.01); H01L 23/552 (2006.01); H01L 29/66 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H03K 17/162 (2013.01); H01L 23/10 (2013.01); H01L 23/495 (2013.01); H01L 23/4952 (2013.01); H01L 23/49541 (2013.01); H01L 23/49548 (2013.01); H01L 23/49562 (2013.01); H01L 23/552 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01); H01L 29/7802 (2013.01); H01L 29/7805 (2013.01); H01L 29/7813 (2013.01); H03K 17/04106 (2013.01); H03K 17/165 (2013.01); H01L 23/3107 (2013.01); H01L 23/49833 (2013.01); H01L 23/49844 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/49113 (2013.01); H01L 2924/00 (2013.01); H01L 2924/13055 (2013.01);
Abstract

The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Qof which a first drain is disposed on the first electrode pattern; a second MISFET Qof which a second drain is disposed on the third electrode pattern; a first control circuit (DG) connected between a first gate Gand a first source Sof the first MISFET, and configured to control a current path conducted from the first source towards the first gate.


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