The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Dec. 20, 2017
Applicant:

Qorvo Us, Inc., Greensboro, NC (US);

Inventors:

Daniel Charles Kerr, Oak Ridge, NC (US);

Jinsung Choi, Greensboro, NC (US);

Baker Scott, San Jose, CA (US);

George Maxim, Saratoga, CA (US);

Hideya Oshima, Santa Clara, CA (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H04B 1/44 (2006.01); H03K 17/693 (2006.01); H03K 17/10 (2006.01);
U.S. Cl.
CPC ...
H03K 17/161 (2013.01); H03K 17/102 (2013.01); H03K 17/162 (2013.01); H03K 17/693 (2013.01); H04B 1/44 (2013.01); H03K 2217/0018 (2013.01); H03K 2217/0054 (2013.01);
Abstract

Disclosed is a transistor-based switch having an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five. The transistor-based switch further includes a gate bias network having a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled to gate terminals of the N number of main FETs. A common gate resistor is coupled between a gate control input and a gate control node of the plurality of gate resistors, and a capacitor is coupled between the gate control node and a switch path node of the main FETs.


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