The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Feb. 23, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Hyunchul Hwang, Suwon-si, KR;

Minsu Kim, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/20 (2006.01); G11C 19/28 (2006.01); G11C 27/02 (2006.01); H03K 3/356 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356121 (2013.01); G11C 11/4074 (2013.01); G11C 19/28 (2013.01); G11C 27/02 (2013.01); H03K 19/20 (2013.01); G11C 11/4076 (2013.01);
Abstract

In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.


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