The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Feb. 13, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Fabio Alessio Marino, San Marcos, CA (US);

Paolo Menegoli, San Jose, CA (US);

Narasimhulu Kanike, San Diego, CA (US);

Francesco Carobolante, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/93 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01G 7/00 (2006.01); H01L 27/08 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 29/93 (2013.01); H01G 7/00 (2013.01); H01L 27/0808 (2013.01); H01L 29/0692 (2013.01); H01L 29/66174 (2013.01); H01L 29/66189 (2013.01); H01L 29/94 (2013.01);
Abstract

Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a semiconductor region, an insulative layer disposed above the semiconductor region, and a first non-insulative region disposed above the insulative layer. In certain aspects, a second non-insulative region is disposed adjacent to the semiconductor region, and a control region is disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region. In certain aspects, the first non-insulative region is disposed above a first portion of the semiconductor region and a second portion of the semiconductor region, and the first portion and the second portion of the semiconductor region are disposed adjacent to a first side and a second side, respectively, of the control region or the second non-insulative region.


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