The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Dec. 20, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyuk Kim, Seongnam-si, KR;

Dae Hyun Jang, Hwaseong-si, KR;

Seung Pil Chung, Seoul, KR;

Sung Il Cho, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 27/11556 (2017.01); H01L 27/11578 (2017.01);
U.S. Cl.
CPC ...
H01L 29/7926 (2013.01); H01L 21/28282 (2013.01); H01L 27/11556 (2013.01); H01L 27/11578 (2013.01); H01L 29/1041 (2013.01); H01L 29/66666 (2013.01); H01L 29/66833 (2013.01);
Abstract

A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.


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