The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Mar. 01, 2017
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Inventor:

Mitsuhiko Kitagawa, Ishikawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/74 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/36 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/94 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7395 (2013.01); H01L 21/743 (2013.01); H01L 29/0696 (2013.01); H01L 29/083 (2013.01); H01L 29/0804 (2013.01); H01L 29/0813 (2013.01); H01L 29/0821 (2013.01); H01L 29/1004 (2013.01); H01L 29/1095 (2013.01); H01L 29/36 (2013.01); H01L 29/407 (2013.01); H01L 29/66181 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01); H01L 29/945 (2013.01);
Abstract

A semiconductor device includes a first electrode, a first semiconductor region disposed on and electrically connected to the first electrode, a second semiconductor region disposed on the first semiconductor region and having a carrier concentration lower than that of the first semiconductor region, a third semiconductor region disposed on the second semiconductor region, a fourth semiconductor region disposed on the third semiconductor region, a fifth semiconductor region disposed on the second semiconductor region and separated from the third semiconductor region in a direction, a gate electrode disposed on the second semiconductor region, facing the third semiconductor region via an insulating layer in the direction and positioned between the third and fourth semiconductor regions, a second electrode disposed on and electrically connected to the fourth semiconductor region, and a third electrode disposed on the fifth semiconductor region, separated from the second electrode, and electrically connected to the fifth semiconductor region.


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