The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Jul. 01, 2016
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Hefei Boe Optoelectronics Technology Co., Ltd., Hefei, Anhui, CN;

Inventors:

Chuanbao Chen, Beijing, CN;

Jie Yang, Beijing, CN;

Xiaobin Yin, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1337 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/1368 (2013.01); G02F 1/133753 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); G02F 2001/134345 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01);
Abstract

An array substrate includes: a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions; a plurality of data lines; a plurality of gate lines intersecting with the plurality of data lines; and a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions; wherein: each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions.


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