The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

May. 30, 2018
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventor:

Reinhold Bayerer, Reichelsheim, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/367 (2006.01); H01L 23/64 (2006.01); H01L 23/66 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H02M 7/00 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76838 (2013.01); H01L 21/76877 (2013.01); H01L 23/367 (2013.01); H01L 23/5386 (2013.01); H01L 23/645 (2013.01); H01L 23/66 (2013.01); H01L 24/49 (2013.01); H01L 25/071 (2013.01); H01L 25/072 (2013.01); H01L 24/48 (2013.01); H01L 2223/6627 (2013.01); H01L 2224/05599 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/19105 (2013.01); H02M 7/003 (2013.01); H05K 3/4608 (2013.01); H05K 3/4617 (2013.01); H05K 2201/10166 (2013.01);
Abstract

A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.


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