The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2019
Filed:
Jul. 03, 2017
Applicant:
SK Hynix Inc., Icheon, KR;
Inventors:
Yong Mi Kim, Hwaseong, KR;
Jae Il Kim, Yongin, KR;
Assignee:
SK HYNIX INC., Icheon, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/12 (2006.01); G06F 11/10 (2006.01); G11C 7/22 (2006.01); G06F 1/12 (2006.01); G11C 29/52 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G06F 1/12 (2013.01); G06F 11/1048 (2013.01); G11C 7/22 (2013.01); G11C 7/1009 (2013.01); G11C 11/4076 (2013.01); G11C 29/52 (2013.01); G11C 2207/229 (2013.01); G11C 2207/2272 (2013.01); G11C 2207/2281 (2013.01);
Abstract
A semiconductor device includes a delay selection signal generation circuit, an internal read signal generation circuit, and an internal write signal generation circuit. The delay selection signal generation circuit generates a delay selection signal in response to an information code signal. The internal read signal generation circuit generates an internal read signal from a mask write signal in response to the delay selection signal and a clock. The internal write signal generation circuit delays the mask write signal by a predetermined delay period to generate an internal write signal.