The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2019

Filed:

Mar. 08, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Sung-Hyun Park, Hwaseong-si, KR;

In-Hak Lee, Daegu, KR;

Jae-Seung Choi, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 7/18 (2006.01); G11C 11/408 (2006.01); H01L 27/11 (2006.01); G11C 7/14 (2006.01); G11C 11/4097 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/14 (2013.01); G11C 7/18 (2013.01); G11C 11/4085 (2013.01); G11C 11/4097 (2013.01); H01L 27/1104 (2013.01);
Abstract

A memory device includes a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell, a complementary bit line connected to the memory cell, an auxiliary bit line, an auxiliary complementary bit line, and a switch circuit. The memory cell stores a single bit. The switch circuit electrically connects one of the bit line and the complementary bit line to one of the auxiliary bit line and the auxiliary complementary bit line, in response to a logic level of a data bit to be written in the memory cell during a write operation, by using at least one or more transistors of at least one dummy cell as a switch, and the at least one dummy cell does not store a data bit.


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